This application is related to Japanese Patent Application No. P2000-060184, filed on Mar. 6, 2000, the entire contents of which are incorporated.
1. Field of the Invention
The present invention relates generally to a transistor, semiconductor devices and a method of manufacturing semiconductors. More particularly, but not exclusively, the present invention relates to metal insulator semiconductor field effect transistor (MISFET) structures. This invention also relates to a method for manufacturing a MISFET.
2. Discussion of the Background
Modem semiconductor microfabrication technologies are developing in a way that makes field effect transistors (FETs) decrease in a minimum feature length. As FETs are miniaturized, gate lengths shrink to almost 0.1 micrometer (xcexcm). This is because size reduction rules are established for achieving both a higher speed performance and a lower power consumption. The miniaturization per se results in a decrease in an occupation area of integrated circuit (IC) components, thus enabling more components to be mounted on a chip. This in turn permits achievement of very-large-scale integration (VLSI) or ultra large-scale integration (VLSI) chips with enhanced multifunctionalities.
Regrettably, it is predictable that the growth in microtechnologies will soon slowdown or stop due to a serious problem which occurs when the minimum feature sizes shrink to 0.1 xcexcm. The problem is that simply miniaturizing IC components cannot lead to successful achievement of higher speed performance. This can be said because further feature size shrinkage results in an increase in parasitic resistances of IC components, which in turn makes it impossible or at least very difficult to increase electrical drivabilities thereof.
One known approach to avoiding this problem is to employ specially designed structures using self-aligned silicide or xe2x80x9csalisidexe2x80x9d techniques or other structures having additional metals as selectively deposited on the source/drain and gate of a FET.
For example, FIG. 26 shows a sectional view of a MISFET using the salicide scheme. This salicide MISFET has on a silicon substrate 1101, an insulated gate electrode 1103 formed thereover with a gate insulation film 1102 interposed between the gate 1103 and the substrate 1101. The gate 1103 has a gate insulation sidewall layer 1104 formed on its side surface. The silicon substrate 1101 has a drain region 1105 formed in its top surface, and a low-resistivity layer 1106 is buried in the drain 1105. The low-resistivity layer 106 is made of a silicide material as low in electrical resistivity as metals. The silicide layer 1106 is self-aligned with an outer vertical surface of the gate insulation sidewall 1104. Here, the drain 1105 is formed by diffusion of an impurity into the substrate 1101. In case the substrate 1101 has a xe2x80x9cpxe2x80x9d conductivity type, the drain 1105 is of an xe2x80x9cnxe2x80x9d type. The substrate 1101 and the drain 1105 form therebetween an interface 1200, at which a p-n junction is formed with a depletion layer interposed. The MISFET also has a source region, not shown, which is similar in structure to the drain region.
With the salicide MISFET, it is possible to reduce resistivities at the source/drain electrodes. Unfortunately, this advantage does not come without accompanying the following penalty. That is, a decrease in the distance between the pn junction 1200 and the silicide 1106 (to about 100 nanometers or less) results in degradation of a rectification in the pn junction, causing a leakage current to begin flowing therein. Once this problem occurs, dynamic random access memory (DRAM) chips employing salicide MISFETs of the type stated above are degraded in data storage retainability characteristics. Further, in logic IC chips, the power consumption can increase. In the worst case, any intended transistor operations are no longer obtainable.
When attempts are made to make the pn junction deeper to avoid the current leakage problem, another problem occurs: the so-called xe2x80x9cshort channelxe2x80x9d effects take place causing transistor threshold potentials to decrease with value irregularities. In brief, to solve these conflicting or xe2x80x9ctrade-offxe2x80x9d problems, the resistivities of the source/drain regions need to be reduced, while at the same time the pn junction needs to be as shallow as possible.
One known approach to lowering the source/drain resistivities while making the pn junction shallower is to employ xe2x80x9csilicide mountxe2x80x9d techniques. More specifically, the source/drain regions are fabricated by selective epitaxial growth (SEG) methods to have an increased thickness. Then, a silicide layer is formed on each of these regions, thereby virtually increasing the effective or xe2x80x9cnetxe2x80x9d distance between the silicide and the pn junction.
One typical salicide-embedded FET structure formed in this way is depicted in cross-section in FIG. 27. This FET has a silicon substrate 1201 and a gate electrode 1203 formed thereover with a gate insulation film 1202 sandwiched between them. The gate electrode 1203 has a dielectric film 1204 (e.g., a gate insulation sidewall) on its sidewall. A drain region 1205 is formed by film growth techniques on the substrate surface. In addition, the drain region 1205 is laterally adjacent to the gate 1203 with the gate insulation sidewall 1204 interposed therebetween. The drain region 1205 has a silicide layer 1206 formed or xe2x80x9cmultilayeredxe2x80x9d on its top surface, and the substrate 1201 and the drain region 1205 are opposite in conductivity type to each other. One example is that the substrate 1201 has p conductivity type, whereas the drain region 1205 has n type. The substrate 1201 and the drain region 1205 form therebetween an interface 1200, at which a pn junction is defined with an associative depletion layer interposed. The FET also has its source region, which is similar in structure to the drain region 1205.
The FET structure of FIG. 27 is suitable for use as a highly miniaturized transistor of the next generation with its gate length of 0.1 xcexcm or below. This can be said because the drain region 1205 may be microfabricated to a demonstrably increased thickness of about 0.1 xcexcm as shown in FIG. 27. This makes it possible to increase the distance between the pn junction 1200 and the silicide 1206. Regrettably, as known to those skilled in the semiconductor device art, such distance increase along with its associated decrease in film thickness of the gate insulation sidewall 1204 results in an increase in resultant parasitic capacitance between the drain region 1205 and the gate electrode 1203. This parasitic capacitance increase causes a problem as to the unavailability of high-speed device performance required, which directly affects an operation speeds of LSIs.
Again, as far as xe2x80x9cfuturexe2x80x9d device""s of the 0.1 xcexcm feature size generation or later generations are concerned, it will be difficult to attain the required resistivity reduction of the source/drain regions or gate without degrading the other transistor characteristics (i.e., while simultaneously achieving short-channel effects with minimized risks of parasitic capacitance increase and at-the-pn-junction current leakage). Additionally, a decrease in channel resistivity due to transistor scaling merely permits further reduction of parasitic resistances.
It should also be noted that traditional salicide processes are performed using selective metal growth techniques. With such selective metal growth, however, very strict process conditions are required for obtaining higher selectivities, resulting in metals being partly formed from time to time on undesired portions of dielectric films. Unintentional metal formation on such xe2x80x9cnon-selectedxe2x80x9d films often results in electrical short-circuiting between the source/drain electrodes. Such electrical shorting also decreases the production yields of semiconductor devices. This problem is becoming more appreciable with a decrease in a minimum feature size of on-chip IC components due to an increase in the number of components per chip. Another problem faced with the selective metal growth methods is that metals employable for increasing selectivities relative to silicon are limited.
Accordingly, one object of the present invention is to solve the above-noted and other problems.
Another object of the present invention is to provide a transistor capable of achieving a channel resistivity phenomena without degrading transistor characteristics even for the 0.1 xcexcm feature size generation or later generations, and also a method of making a semiconductor device having a sufficiently low contact resistivity at the source/drain and gate electrodes thereof.
Yet another object of the present invention to provide a method for manufacturing a semiconductor device capable of avoiding the use of selective metal growth techniques and permitting the use of any desired types of metals for the source/drain and gate electrodes.
To achieve these and other objects, the present invention provides a transistor including a semiconductor substrate, a gate insulation film formed on the semiconductor substrate, a gate electrode formed on the gate insulation film, and a channel region formed in the semiconductor substrate below the gate insulation film. Also included is a source region and a drain region formed to be spaced apart from each other in the semiconductor substrate and in which the channel region is between the source region and the drain region. Further, a source semiconductor layer is formed over the source region and has a concave portion at an upper portion thereof and an acute angle defined between a side face of the source semiconductor layer facing the gate electrode and a surface of the semiconductor substrate. A drain semiconductor layer is also formed over the drain region and has a concave portion at an upper portion thereof and an acute angle defined between a side face of the drain semiconductor layer facing the gate electrode and a surface of the semiconductor substrate. In addition, a source electrode is formed at the concave portion at the upper portion of the source semiconductor layer, and a drain electrode is formed at the concave portion at the upper portion of the drain semiconductor layer.
The present invention also provides a semiconductor device including an n-channel and a p-channel MISFET on a common semiconductor substrate. The n-channel and p-channel MISFETs have the concave portions and acute angles as discussed above.
Further, in one example of the present invention, the source electrode and the drain electrode of the n-channel MISFET include a different material from the source electrode and the drain electrode of the p-channel MISFET.
In another example of the present invention, the gate electrode of the n-channel MISFET includes a different material from the gate electrode of the p-channel MISFET.
The present invention also provides a method of manufacturing a semiconductor device, which includes forming a first dielectric film on a semiconductor substrate, depositing a first semiconductor layer on the first dielectric film, patterning the first dielectric film and the first semiconductor layer, forming second semiconductor layers of first and second conductivity types on a principal surface of the semiconductor substrate, and depositing a second dielectric film on the first dielectric film and the first semiconductor layer plus the second semiconductor layers. The method also includes removing the second dielectric film until upper faces of the first semiconductor layer and the second semiconductor layers appear, removing the first semiconductor layer and the second semiconductor layers while letting at least part of the second semiconductor layers reside, and depositing a metal or silicide on the second semiconductor layers.
In addition, a gas or vapor phase growth of the second semiconductor layers makes it possible to form a facet on the side face opposing the gate electrode. At this time, it is possible to adjust the inclination or gradient of this facet by selection of the growth surface of the semiconductor substrate at an appropriate crystal plane orientation.
Another advantage lies in an ability to reduce the parasitic resistance without having to negatively effect the remaining transistor characteristics (such as short-channel effect, parasitic capacitance increase, and at-the-pn-junction current leakage).
The present invention also provides a technique for fabricating the source/drain and gate electrodes by a method including the steps of first forming recess portions, forming a metal on the overall surface, and then let this be subject to etch-back processing. This fabrication method no longer requires the use of traditional selective metal growth processes. Accordingly, the resultant device structure is free from risks of electrical shorting between the source and drain electrodes without depending on selective growth abilities of metals used. Thus, it is possible to improve manufacturing yields.